Small pitch packages and high reliability printed circuit boards
The silicon die of active electronic components are with rare exceptions mounted in packages for mechanical support and solder connection to Printed Circuit Boards (PCBs). For processors, FPGAs and other components with very high number of connections, the dominant package is the Ball Grid Array, or BGA. In a BGA the traditional component pins around the edge of the package is replaced by an array of solder bumps underneath the package which is then mounted to a PCB by reflow soldering. Packages with solder bumps emerged from the Pin Grid Array (PGA) as miniaturization made the pins fragile and difficult to mount without bending.
Packages with solder bumps were used in high-end computer systems by the mid 1980’s, while the first series produced BGAs made it onto PC-boards in 1992. BGAs with well over 1000 individual connections are commonplace today, and there are examples of packages with more than 2000 solder bumps. In addition to the size of the array, the BGA is characterized by its pitch; the centre to centre spacing between solder bumps in the x and y directions. While the first BGAs had a pitch of 1.78mm (50mil), 1mm has been a common pitch for a long time. The consumer segment has long since made the transition to sub-millimeter pitch (0.65mm, 0.4mm or even smaller). driven by increased pin count due to higher levels of integration, and the demand for miniaturization. However, sub-millimeter pitch BGAs creates real challenges for products that require high reliability.
IPC Performance classes
Institute of Printed Circuits or IPC is an international industry organization serving those who design and manufacture printed boards and assemblies. It is widely known as an issuer of standards on all aspects of printed boards. The standard IPC-6011 defines generic performance specifications for printed boards, and it establishes 3 performance classes of products:
Class 1 General Electronic Products – Includes consumer products, some computer and computer peripherals suitable for applications where cosmetic imperfection is not important and the major requirement is function of the completed assembly.
Class 2 Dedicated Service Electronic Products – Includes communications equipment, sophisticated business machines, instruments where high performance and extended life is required and for which uninterrupted service is desired but not critical. Certain cosmetic imperfections are allowed.
Class 3 High Reliability Electronic Products – Includes the equipment and products where continued performance or performance-on-demand is critical. Equipment downtime cannot be tolerated and must function when required, such as life support items or flight control systems. Printed boards in this class are suitable for applications where high levels of assurance are required and service is essential.
Circuit board specifications usually make reference to standards issued by IPC. IPC-6011 establishes three performance classes distinguished by the reliability requirements for each (see above box).
Class 3 is for products where downtime cannot be tolerated or where the end-user environment is uncommonly harsh. It is the equipment vendor who decides which class a PCB should be manufactured to, sometimes guided by customer requirements.
The acceptance criteria for Class 3 are significantly more difficult to meet than for Class 2, and a massive process monitoring and test regime must be followed by the PCB manufacturer. Hence a Class 3 PCB may well cost 10 times more than an identical board manufactured to Class 2 requirements. No matter the cost; a PCB cannot be manufactured to Class 3 requirements unless it is designed for it.
The incompatibility between Class 3 requirements and small-pitch BGAs arise from the so-called via. The via makes connections between different layers of a PCB possible, and is formed by plating a hole through pads on outside layers of the board and on any other layer that require a connection.
A reasonably advanced PCB today comprises between 10 and 20 layers of copper separated by fiberglass or another dielectric material. Electrical connections on each layer are made by etched copper tracks while vertical connections between layers are accomplished by a fabricated feature called via. Vias are formed by drilling holes in the laminated PCB prior to etching of the outer layers. The walls of the drilled holes are then plated to form a copper barrel through the board. Pads and tracks intercepting the drill perimeter make connections to the copper barrel. The outer layers are then etched to complete the circuit before the board continues through the finishing processes.
Cracks between the pads and the copper barrel is one of the major reliability concerns related to Printed Circuit Boards, particularly PCBs that require a lead-free process. Class 3 differ from the other classes on the relation between the via pad and the drilled hole. The drill bit will generally not hit each pad in the nominal centre due to production tolerances.
In Class 2 the drill is allowed to partly miss any pad as long as a defined majority of the drill falls within the pad perimeter (so-called breakout). The plating process will still assure electrical connection where required. Class 3, on the other hand, not only require that he entire drill falls within the perimeter of every pad, but even demands a guard band of 50μm, a so-called annular ring. As a consequence a Class 3 via pad is larger than a Class2 pad for a given drill diameter and process tolerance.
IPC-2221 is the design standard that provides guidance on the dimensions of via pads based on drill diameter and other design and production parameters. Assuming a very small but still reasonably available drill diameter of 0.3mm, and assuming the highest level of Producibility (Level C, tight tolerances) the recommended pad diameter is 0.6mm.
On every layer where a connection to the via is not required, copper must be voided in radius around the nominal centre in order to avoid accidental connection. This so-called antipad is always bigger than the pads of the via. In the PCB under a BGA there will, at least in some areas, be a grid of vias with centre to centre spacing equal to that of the BGA. Class 3 pads on a 0.8mm grid will only leave 0.2mm airgap between the pads,not enough to allow for routing of traces between the pads considering that tracks and spacing also must allow for Class 3 production.
As a consequence it is not possible to route connections out of the BGA area. While 0.8mm pitch pushes the limit of a class 3 design, a 0.75mm og 0.65mm pitch is out of reach completely. A secondary problem is the large antipads on power and ground planes which perforates these planes to such an extent that Power Integrity suffers.
This state of affairs is a classic example of a standard lagging behind technology development. So what can we do to remedy the situation in the meantime? One approach is to avoid selecting components in BGA packages with pitch smaller than 1mm. This strategy has an expiry date as the selection of available components will be unacceptably limited over time.
As an example the popular and versatile processor series i.MX from Freescale is already now only available in packages of 0.8mm pitch or less. Another approach is to try and push the technology limit in terms of tolerances and line and track spacing. It carries a high cost as it limits the choice of PCB manufacturers able to produce the boards and will in any case incur the cost of a higher yield loss in addition to the heightened risk of forcing the manufacturers to operate at the limit of their capability.
The only viable solution in the longer term is to make judicious and informed use of the technology known as High Density Interconnect (HDI) using laser drilled microvias. Clever application of HDI demands a high level of process knowledge by the designer, and is the topic of an article in a later issue of Interrupt Inside.
Next article in this series
High density interconnect (hdi) is defined as printed circuit boards with higher wiring density than conventional boards. A central feature of hdi is the microvia, blind vias defined by hole diameters smaller than 150μm and normally drilled by laser. The microvia is by many considered an exotic and expensive feature with poor reliability to be avoided unless the package density leaves no other alternatives. But in the consumer segment hdi is actively used to reduce cost and in a given case the use of microvias may even improve reliability. In the hands of knowledgeable designers microvias are also used to improve signal and power integrity, and to improve noise and emc performance. While conventional printed circuit boards often are specified in general terms, hdi requires decisions on the part of the designer that calls for detailed knowledge of materials and production processes. We take a closer look at hdi in the next issue of interrupt inside.